8-bit Microprocessor Verilog Code -

// Memory interface assign addr_bus = (state == FETCH) ? pc : ((state == MEM_READ || state == MEM_WRITE) ? ir[7:0], reg_b : 16'hzzzz); assign data_bus = (state == MEM_WRITE) ? reg_a : 8'hzz; assign mem_read = (state == FETCH || state == MEM_READ); assign mem_write = (state == MEM_WRITE);

// Control FSM states reg [2:0] state; localparam FETCH = 3'b000, DECODE = 3'b001, EXECUTE = 3'b010, MEM_READ = 3'b011, MEM_WRITE = 3'b100;

reg_file reg_inst (.clk(clk), .rst(rst), .reg_sel_a(reg_sel_a), .reg_sel_b(reg_sel_b), .reg_sel_wr(reg_sel_wr), .wr_data(wr_data), .wr_en(wr_en), .reg_a_out(reg_a), .reg_b_out(reg_b));

module processor_tb; reg clk, rst; wire [15:0] addr; wire [7:0] data; wire mem_read, mem_write; processor uut (.clk(clk), .rst(rst), .addr_bus(addr), .data_bus(data), .mem_read(mem_read), .mem_write(mem_write));

always #5 clk = ~clk;

// Instantiate modules alu alu_inst (.a(reg_a), .b(reg_b), .op(alu_op), .result(alu_result), .zero(alu_zero));